first commit
This commit is contained in:
Lazarewicz Julien
19
RF24configs/README
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19
RF24configs/README
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This directory contains a selection of radio configuiration files for use by RH_RF24.cpp
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They were generated by Silicon Labs Wireless Development Suite (WDS) 3.2.11.0
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The configuration file controls all the basic frequency aand modulation parameters for the radio.
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The appropriate one for your application or sketch must be #included by RH_RF24.cpp
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You can generate your own custom configuration file by generatng a new one with WDS,
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copying it to this directory with a unique anme and #include it in RH_RF24.cpp
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The file names encode the basic parameters:
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radio_config_Siaaaa_bb_ccc_dddd_ee_ff_gg.h
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where
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aaaa = Chip typenukber eg 4464
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bb = Crytsyal frequency in MHz
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ccc = RF base frequency in MHz
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dddd = Modulation type eg 2GFSK
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ee = Data rate in kbps
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ff = Deviation in kHz
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516
RF24configs/radio_config_Si4464_27_434_2GFSK_5_10.h
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516
RF24configs/radio_config_Si4464_27_434_2GFSK_5_10.h
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@@ -0,0 +1,516 @@
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/*! @file radio_config.h
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* @brief This file contains the automatically generated
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* configurations.
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*
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* @n WDS GUI Version: 3.2.11.0
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* @n Device: Si4464 Rev.: B1
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*
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* @b COPYRIGHT
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* @n Silicon Laboratories Confidential
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* @n Copyright 2017 Silicon Laboratories, Inc.
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* @n http://www.silabs.com
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*/
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#ifndef RADIO_CONFIG_H_
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#define RADIO_CONFIG_H_
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// USER DEFINED PARAMETERS
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// Define your own parameters here
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// INPUT DATA
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/*
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// Crys_freq(Hz): 27000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
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// MOD_type: 3 Rsymb(sps): 5000 Fdev(Hz): 10000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
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// RF Freq.(MHz): 434 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
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//
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// # RX IF frequency is -421875 Hz
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// # WB filter 2 (BW = 61.84 kHz); NB-filter 2 (BW = 61.84 kHz)
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//
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// Modulation index: 4
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*/
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// CONFIGURATION PARAMETERS
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#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 27000000L
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#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
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#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
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#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
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#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
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// CONFIGURATION COMMANDS
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/*
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// Command: RF_POWER_UP
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// Description: Command to power-up the device and select the operational mode and functionality.
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*/
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#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x9B, 0xFC, 0xC0
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/*
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// Command: RF_GPIO_PIN_CFG
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// Description: Configures the GPIO pins.
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*/
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#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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/*
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// Set properties: RF_GLOBAL_XO_TUNE_2
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// Number of properties: 2
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// Group ID: 0x00
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// Start ID: 0x00
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// Default values: 0x40, 0x00,
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// Descriptions:
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// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
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// GLOBAL_CLK_CFG - Clock configuration options.
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*/
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#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
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/*
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// Set properties: RF_GLOBAL_CONFIG_1
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// Number of properties: 1
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// Group ID: 0x00
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// Start ID: 0x03
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// Default values: 0x20,
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// Descriptions:
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// GLOBAL_CONFIG - Global configuration settings.
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*/
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#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
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/*
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// Set properties: RF_INT_CTL_ENABLE_2
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// Number of properties: 2
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// Group ID: 0x01
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// Start ID: 0x00
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// Default values: 0x04, 0x00,
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// Descriptions:
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// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
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// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
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*/
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#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
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/*
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// Set properties: RF_FRR_CTL_A_MODE_4
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// Number of properties: 4
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// Group ID: 0x02
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// Start ID: 0x00
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// Default values: 0x01, 0x02, 0x09, 0x00,
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// Descriptions:
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// FRR_CTL_A_MODE - Fast Response Register A Configuration.
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// FRR_CTL_B_MODE - Fast Response Register B Configuration.
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// FRR_CTL_C_MODE - Fast Response Register C Configuration.
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// FRR_CTL_D_MODE - Fast Response Register D Configuration.
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*/
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#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
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/*
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// Set properties: RF_PREAMBLE_TX_LENGTH_1
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// Number of properties: 1
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// Group ID: 0x10
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// Start ID: 0x00
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// Default values: 0x08,
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// Descriptions:
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// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
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*/
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#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
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/*
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// Set properties: RF_PREAMBLE_CONFIG_1
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// Number of properties: 1
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// Group ID: 0x10
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// Start ID: 0x04
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// Default values: 0x21,
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// Descriptions:
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// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
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*/
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#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
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/*
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// Set properties: RF_SYNC_CONFIG_3
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// Number of properties: 3
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// Group ID: 0x11
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// Start ID: 0x00
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// Default values: 0x01, 0x2D, 0xD4,
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// Descriptions:
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// SYNC_CONFIG - Sync Word configuration bits.
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// SYNC_BITS_31_24 - Sync word.
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// SYNC_BITS_23_16 - Sync word.
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*/
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#define RF_SYNC_CONFIG_3 0x11, 0x11, 0x03, 0x00, 0x01, 0xB4, 0x2B
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/*
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// Set properties: RF_PKT_CONFIG1_1
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// Number of properties: 1
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// Group ID: 0x12
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// Start ID: 0x06
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// Default values: 0x00,
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// Descriptions:
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// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
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*/
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#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x02
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/*
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// Set properties: RF_PKT_FIELD_1_CONFIG_1
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// Number of properties: 1
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// Group ID: 0x12
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// Start ID: 0x0F
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// Default values: 0x00,
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// Descriptions:
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// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
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*/
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#define RF_PKT_FIELD_1_CONFIG_1 0x11, 0x12, 0x01, 0x0F, 0x04
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/*
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// Set properties: RF_MODEM_MOD_TYPE_12
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// Number of properties: 12
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// Group ID: 0x20
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// Start ID: 0x00
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// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
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// Descriptions:
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// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
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// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
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// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
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// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
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// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
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// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
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// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
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// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
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// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
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// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
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// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
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// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
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*/
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#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x03, 0x0D, 0x40, 0x05, 0x9B, 0xFC, 0xC0, 0x00, 0x03
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/*
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// Set properties: RF_MODEM_FREQ_DEV_0_1
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// Number of properties: 1
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// Group ID: 0x20
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// Start ID: 0x0C
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// Default values: 0xD3,
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// Descriptions:
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// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
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*/
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#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x09
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/*
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// Set properties: RF_MODEM_TX_RAMP_DELAY_8
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// Number of properties: 8
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// Group ID: 0x20
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// Start ID: 0x18
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// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
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// Descriptions:
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// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
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// MODEM_MDM_CTRL - MDM control.
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// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
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// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
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// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
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// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
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// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
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// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
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*/
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#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x10
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/*
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// Set properties: RF_MODEM_BCR_OSR_1_9
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// Number of properties: 9
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// Group ID: 0x20
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// Start ID: 0x22
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// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
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// Descriptions:
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// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
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// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
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// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
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// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
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// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
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// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
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// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
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// MODEM_BCR_GEAR - RX BCR loop gear control.
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// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
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*/
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#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0xC2, 0x01, 0x23, 0x45, 0x00, 0x92, 0x02, 0xC2
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/*
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// Set properties: RF_MODEM_AFC_GEAR_7
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// Number of properties: 7
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// Group ID: 0x20
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// Start ID: 0x2C
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// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
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// Descriptions:
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// MODEM_AFC_GEAR - RX AFC loop gear control.
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// MODEM_AFC_WAIT - RX AFC loop wait time control.
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// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
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// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
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// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
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// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
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// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
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*/
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#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x10, 0x18, 0x36, 0x80
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/*
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// Set properties: RF_MODEM_AGC_CONTROL_1
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// Number of properties: 1
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// Group ID: 0x20
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// Start ID: 0x35
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// Default values: 0xE0,
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// Descriptions:
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// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
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*/
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#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
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/*
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// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
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// Number of properties: 9
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// Group ID: 0x20
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// Start ID: 0x38
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// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
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// Descriptions:
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// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
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// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
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// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
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// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
|
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// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
|
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// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
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// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
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// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
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// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
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*/
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#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x62, 0x62, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2A
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/*
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// Set properties: RF_MODEM_OOK_CNT1_8
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// Number of properties: 8
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// Group ID: 0x20
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||||
// Start ID: 0x42
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// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80,
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// Descriptions:
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// MODEM_OOK_CNT1 - OOK control.
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// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
|
||||
// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
|
||||
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
|
||||
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
|
||||
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
|
||||
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
|
||||
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
|
||||
*/
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||||
#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0x90, 0x01, 0x80
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|
||||
/*
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||||
// Set properties: RF_MODEM_RSSI_COMP_1
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||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x4E
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||||
// Default values: 0x32,
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||||
// Descriptions:
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// MODEM_RSSI_COMP - RSSI compensation value.
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||||
*/
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#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
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||||
/*
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||||
// Set properties: RF_MODEM_CLKGEN_BAND_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x51
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
|
||||
*/
|
||||
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x00
|
||||
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x18
|
||||
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PA_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x22
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08, 0x7F, 0x00, 0x5D,
|
||||
// Descriptions:
|
||||
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
|
||||
// PA_PWR_LVL - Configuration of PA output power level.
|
||||
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
|
||||
// PA_TC - Configuration of PA ramping parameters.
|
||||
*/
|
||||
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNTH_PFDCP_CPFF_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x23
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
|
||||
// Descriptions:
|
||||
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
|
||||
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
|
||||
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
|
||||
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
|
||||
*/
|
||||
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_FREQ_CONTROL_INTE_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x40
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
|
||||
// Descriptions:
|
||||
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
|
||||
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
|
||||
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
|
||||
*/
|
||||
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3F, 0x0A, 0x5E, 0xD0, 0x4B, 0xDA, 0x20, 0xFE
|
||||
|
||||
|
||||
// AUTOMATICALLY GENERATED CODE!
|
||||
// DO NOT EDIT/MODIFY BELOW THIS LINE!
|
||||
// --------------------------------------------
|
||||
|
||||
#ifndef FIRMWARE_LOAD_COMPILE
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { \
|
||||
0x07, RF_POWER_UP, \
|
||||
0x08, RF_GPIO_PIN_CFG, \
|
||||
0x06, RF_GLOBAL_XO_TUNE_2, \
|
||||
0x05, RF_GLOBAL_CONFIG_1, \
|
||||
0x06, RF_INT_CTL_ENABLE_2, \
|
||||
0x08, RF_FRR_CTL_A_MODE_4, \
|
||||
0x05, RF_PREAMBLE_TX_LENGTH_1, \
|
||||
0x05, RF_PREAMBLE_CONFIG_1, \
|
||||
0x07, RF_SYNC_CONFIG_3, \
|
||||
0x05, RF_PKT_CONFIG1_1, \
|
||||
0x05, RF_PKT_FIELD_1_CONFIG_1, \
|
||||
0x10, RF_MODEM_MOD_TYPE_12, \
|
||||
0x05, RF_MODEM_FREQ_DEV_0_1, \
|
||||
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
|
||||
0x0D, RF_MODEM_BCR_OSR_1_9, \
|
||||
0x0B, RF_MODEM_AFC_GEAR_7, \
|
||||
0x05, RF_MODEM_AGC_CONTROL_1, \
|
||||
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
|
||||
0x0C, RF_MODEM_OOK_CNT1_8, \
|
||||
0x05, RF_MODEM_RSSI_COMP_1, \
|
||||
0x05, RF_MODEM_CLKGEN_BAND_1, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
|
||||
0x08, RF_PA_MODE_4, \
|
||||
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
|
||||
0x0C, RF_FREQ_CONTROL_INTE_8, \
|
||||
0x00 \
|
||||
}
|
||||
#else
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
|
||||
#endif
|
||||
|
||||
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
|
||||
#error "This property must be defined!"
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
|
||||
#endif
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA { \
|
||||
Radio_Configuration_Data_Array, \
|
||||
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
|
||||
}
|
||||
|
||||
#endif /* RADIO_CONFIG_H_ */
|
||||
516
RF24configs/radio_config_Si4464_30_434_2GFSK_10_20.h
Normal file
516
RF24configs/radio_config_Si4464_30_434_2GFSK_10_20.h
Normal file
@@ -0,0 +1,516 @@
|
||||
/*! @file radio_config.h
|
||||
* @brief This file contains the automatically generated
|
||||
* configurations.
|
||||
*
|
||||
* @n WDS GUI Version: 3.2.11.0
|
||||
* @n Device: Si4464 Rev.: B1
|
||||
*
|
||||
* @b COPYRIGHT
|
||||
* @n Silicon Laboratories Confidential
|
||||
* @n Copyright 2017 Silicon Laboratories, Inc.
|
||||
* @n http://www.silabs.com
|
||||
*/
|
||||
|
||||
#ifndef RADIO_CONFIG_H_
|
||||
#define RADIO_CONFIG_H_
|
||||
|
||||
// USER DEFINED PARAMETERS
|
||||
// Define your own parameters here
|
||||
|
||||
// INPUT DATA
|
||||
/*
|
||||
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
|
||||
// MOD_type: 3 Rsymb(sps): 10000 Fdev(Hz): 20000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
|
||||
// RF Freq.(MHz): 434 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
|
||||
//
|
||||
// # RX IF frequency is -468750 Hz
|
||||
// # WB filter 4 (BW = 82.64 kHz); NB-filter 4 (BW = 82.64 kHz)
|
||||
//
|
||||
// Modulation index: 4
|
||||
*/
|
||||
|
||||
|
||||
// CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
|
||||
|
||||
|
||||
// CONFIGURATION COMMANDS
|
||||
|
||||
/*
|
||||
// Command: RF_POWER_UP
|
||||
// Description: Command to power-up the device and select the operational mode and functionality.
|
||||
*/
|
||||
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
|
||||
|
||||
/*
|
||||
// Command: RF_GPIO_PIN_CFG
|
||||
// Description: Configures the GPIO pins.
|
||||
*/
|
||||
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_XO_TUNE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x40, 0x00,
|
||||
// Descriptions:
|
||||
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
|
||||
// GLOBAL_CLK_CFG - Clock configuration options.
|
||||
*/
|
||||
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x03
|
||||
// Default values: 0x20,
|
||||
// Descriptions:
|
||||
// GLOBAL_CONFIG - Global configuration settings.
|
||||
*/
|
||||
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
|
||||
|
||||
/*
|
||||
// Set properties: RF_INT_CTL_ENABLE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x01
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x04, 0x00,
|
||||
// Descriptions:
|
||||
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
|
||||
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
|
||||
*/
|
||||
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_FRR_CTL_A_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x02
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x02, 0x09, 0x00,
|
||||
// Descriptions:
|
||||
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
|
||||
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
|
||||
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
|
||||
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
|
||||
*/
|
||||
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_TX_LENGTH_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
|
||||
*/
|
||||
#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x04
|
||||
// Default values: 0x21,
|
||||
// Descriptions:
|
||||
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
|
||||
*/
|
||||
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNC_CONFIG_3
|
||||
// Number of properties: 3
|
||||
// Group ID: 0x11
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x2D, 0xD4,
|
||||
// Descriptions:
|
||||
// SYNC_CONFIG - Sync Word configuration bits.
|
||||
// SYNC_BITS_31_24 - Sync word.
|
||||
// SYNC_BITS_23_16 - Sync word.
|
||||
*/
|
||||
#define RF_SYNC_CONFIG_3 0x11, 0x11, 0x03, 0x00, 0x01, 0xB4, 0x2B
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_CONFIG1_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x06
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
|
||||
*/
|
||||
#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_FIELD_1_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x0F
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
|
||||
*/
|
||||
#define RF_PKT_FIELD_1_CONFIG_1 0x11, 0x12, 0x01, 0x0F, 0x04
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_MOD_TYPE_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
|
||||
// Descriptions:
|
||||
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
|
||||
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
|
||||
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
|
||||
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
|
||||
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x06, 0x1A, 0x80, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x05
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_FREQ_DEV_0_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xD3,
|
||||
// Descriptions:
|
||||
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x76
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x18
|
||||
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
|
||||
// Descriptions:
|
||||
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
|
||||
// MODEM_MDM_CTRL - MDM control.
|
||||
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
|
||||
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
*/
|
||||
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_BCR_OSR_1_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x22
|
||||
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
|
||||
// Descriptions:
|
||||
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GEAR - RX BCR loop gear control.
|
||||
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
|
||||
*/
|
||||
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0x77, 0x01, 0x5D, 0x86, 0x00, 0xAF, 0x02, 0xC2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AFC_GEAR_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x2C
|
||||
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
|
||||
// Descriptions:
|
||||
// MODEM_AFC_GEAR - RX AFC loop gear control.
|
||||
// MODEM_AFC_WAIT - RX AFC loop wait time control.
|
||||
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
|
||||
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
|
||||
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
|
||||
*/
|
||||
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x1D, 0x10, 0x04, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_CONTROL_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x35
|
||||
// Default values: 0xE0,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
|
||||
*/
|
||||
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x38
|
||||
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
|
||||
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
|
||||
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
|
||||
// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
|
||||
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
|
||||
*/
|
||||
#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x52, 0x52, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_OOK_CNT1_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x42
|
||||
// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80,
|
||||
// Descriptions:
|
||||
// MODEM_OOK_CNT1 - OOK control.
|
||||
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
|
||||
// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
|
||||
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
|
||||
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
|
||||
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
|
||||
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
|
||||
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
|
||||
*/
|
||||
#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0xAD, 0x01, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_RSSI_COMP_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x4E
|
||||
// Default values: 0x32,
|
||||
// Descriptions:
|
||||
// MODEM_RSSI_COMP - RSSI compensation value.
|
||||
*/
|
||||
#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CLKGEN_BAND_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x51
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
|
||||
*/
|
||||
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x00
|
||||
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00, 0xA2, 0x81, 0x26, 0xAF, 0x3F, 0xEE
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x18
|
||||
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xC8, 0xC7, 0xDB, 0xF2, 0x02, 0x08, 0x07, 0x03, 0x15, 0xFC, 0x0F, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PA_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x22
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08, 0x7F, 0x00, 0x5D,
|
||||
// Descriptions:
|
||||
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
|
||||
// PA_PWR_LVL - Configuration of PA output power level.
|
||||
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
|
||||
// PA_TC - Configuration of PA ramping parameters.
|
||||
*/
|
||||
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNTH_PFDCP_CPFF_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x23
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
|
||||
// Descriptions:
|
||||
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
|
||||
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
|
||||
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
|
||||
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
|
||||
*/
|
||||
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_FREQ_CONTROL_INTE_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x40
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
|
||||
// Descriptions:
|
||||
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
|
||||
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
|
||||
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
|
||||
*/
|
||||
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0E, 0xEE, 0xEE, 0x44, 0x44, 0x20, 0xFE
|
||||
|
||||
|
||||
// AUTOMATICALLY GENERATED CODE!
|
||||
// DO NOT EDIT/MODIFY BELOW THIS LINE!
|
||||
// --------------------------------------------
|
||||
|
||||
#ifndef FIRMWARE_LOAD_COMPILE
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { \
|
||||
0x07, RF_POWER_UP, \
|
||||
0x08, RF_GPIO_PIN_CFG, \
|
||||
0x06, RF_GLOBAL_XO_TUNE_2, \
|
||||
0x05, RF_GLOBAL_CONFIG_1, \
|
||||
0x06, RF_INT_CTL_ENABLE_2, \
|
||||
0x08, RF_FRR_CTL_A_MODE_4, \
|
||||
0x05, RF_PREAMBLE_TX_LENGTH_1, \
|
||||
0x05, RF_PREAMBLE_CONFIG_1, \
|
||||
0x07, RF_SYNC_CONFIG_3, \
|
||||
0x05, RF_PKT_CONFIG1_1, \
|
||||
0x05, RF_PKT_FIELD_1_CONFIG_1, \
|
||||
0x10, RF_MODEM_MOD_TYPE_12, \
|
||||
0x05, RF_MODEM_FREQ_DEV_0_1, \
|
||||
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
|
||||
0x0D, RF_MODEM_BCR_OSR_1_9, \
|
||||
0x0B, RF_MODEM_AFC_GEAR_7, \
|
||||
0x05, RF_MODEM_AGC_CONTROL_1, \
|
||||
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
|
||||
0x0C, RF_MODEM_OOK_CNT1_8, \
|
||||
0x05, RF_MODEM_RSSI_COMP_1, \
|
||||
0x05, RF_MODEM_CLKGEN_BAND_1, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
|
||||
0x08, RF_PA_MODE_4, \
|
||||
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
|
||||
0x0C, RF_FREQ_CONTROL_INTE_8, \
|
||||
0x00 \
|
||||
}
|
||||
#else
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
|
||||
#endif
|
||||
|
||||
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
|
||||
#error "This property must be defined!"
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
|
||||
#endif
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA { \
|
||||
Radio_Configuration_Data_Array, \
|
||||
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
|
||||
}
|
||||
|
||||
#endif /* RADIO_CONFIG_H_ */
|
||||
516
RF24configs/radio_config_Si4464_30_434_2GFSK_5_10.h
Normal file
516
RF24configs/radio_config_Si4464_30_434_2GFSK_5_10.h
Normal file
@@ -0,0 +1,516 @@
|
||||
/*! @file radio_config.h
|
||||
* @brief This file contains the automatically generated
|
||||
* configurations.
|
||||
*
|
||||
* @n WDS GUI Version: 3.2.11.0
|
||||
* @n Device: Si4464 Rev.: B1
|
||||
*
|
||||
* @b COPYRIGHT
|
||||
* @n Silicon Laboratories Confidential
|
||||
* @n Copyright 2017 Silicon Laboratories, Inc.
|
||||
* @n http://www.silabs.com
|
||||
*/
|
||||
|
||||
#ifndef RADIO_CONFIG_H_
|
||||
#define RADIO_CONFIG_H_
|
||||
|
||||
// USER DEFINED PARAMETERS
|
||||
// Define your own parameters here
|
||||
|
||||
// INPUT DATA
|
||||
/*
|
||||
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
|
||||
// MOD_type: 3 Rsymb(sps): 5000 Fdev(Hz): 10000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
|
||||
// RF Freq.(MHz): 434 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
|
||||
//
|
||||
// # RX IF frequency is -468750 Hz
|
||||
// # WB filter 1 (BW = 57.23 kHz); NB-filter 1 (BW = 57.23 kHz)
|
||||
//
|
||||
// Modulation index: 4
|
||||
*/
|
||||
|
||||
|
||||
// CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
|
||||
|
||||
|
||||
// CONFIGURATION COMMANDS
|
||||
|
||||
/*
|
||||
// Command: RF_POWER_UP
|
||||
// Description: Command to power-up the device and select the operational mode and functionality.
|
||||
*/
|
||||
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
|
||||
|
||||
/*
|
||||
// Command: RF_GPIO_PIN_CFG
|
||||
// Description: Configures the GPIO pins.
|
||||
*/
|
||||
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_XO_TUNE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x40, 0x00,
|
||||
// Descriptions:
|
||||
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
|
||||
// GLOBAL_CLK_CFG - Clock configuration options.
|
||||
*/
|
||||
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x03
|
||||
// Default values: 0x20,
|
||||
// Descriptions:
|
||||
// GLOBAL_CONFIG - Global configuration settings.
|
||||
*/
|
||||
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
|
||||
|
||||
/*
|
||||
// Set properties: RF_INT_CTL_ENABLE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x01
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x04, 0x00,
|
||||
// Descriptions:
|
||||
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
|
||||
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
|
||||
*/
|
||||
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_FRR_CTL_A_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x02
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x02, 0x09, 0x00,
|
||||
// Descriptions:
|
||||
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
|
||||
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
|
||||
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
|
||||
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
|
||||
*/
|
||||
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_TX_LENGTH_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
|
||||
*/
|
||||
#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x04
|
||||
// Default values: 0x21,
|
||||
// Descriptions:
|
||||
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
|
||||
*/
|
||||
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNC_CONFIG_3
|
||||
// Number of properties: 3
|
||||
// Group ID: 0x11
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x2D, 0xD4,
|
||||
// Descriptions:
|
||||
// SYNC_CONFIG - Sync Word configuration bits.
|
||||
// SYNC_BITS_31_24 - Sync word.
|
||||
// SYNC_BITS_23_16 - Sync word.
|
||||
*/
|
||||
#define RF_SYNC_CONFIG_3 0x11, 0x11, 0x03, 0x00, 0x01, 0xB4, 0x2B
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_CONFIG1_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x06
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
|
||||
*/
|
||||
#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_FIELD_1_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x0F
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
|
||||
*/
|
||||
#define RF_PKT_FIELD_1_CONFIG_1 0x11, 0x12, 0x01, 0x0F, 0x04
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_MOD_TYPE_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
|
||||
// Descriptions:
|
||||
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
|
||||
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
|
||||
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
|
||||
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
|
||||
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x03, 0x0D, 0x40, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_FREQ_DEV_0_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xD3,
|
||||
// Descriptions:
|
||||
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xBB
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x18
|
||||
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
|
||||
// Descriptions:
|
||||
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
|
||||
// MODEM_MDM_CTRL - MDM control.
|
||||
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
|
||||
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
*/
|
||||
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x30, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_BCR_OSR_1_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x22
|
||||
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
|
||||
// Descriptions:
|
||||
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GEAR - RX BCR loop gear control.
|
||||
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
|
||||
*/
|
||||
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0x77, 0x01, 0x5D, 0x86, 0x00, 0xAF, 0x02, 0xC2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AFC_GEAR_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x2C
|
||||
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
|
||||
// Descriptions:
|
||||
// MODEM_AFC_GEAR - RX AFC loop gear control.
|
||||
// MODEM_AFC_WAIT - RX AFC loop wait time control.
|
||||
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
|
||||
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
|
||||
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
|
||||
*/
|
||||
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x0F, 0x15, 0x87, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_CONTROL_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x35
|
||||
// Default values: 0xE0,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
|
||||
*/
|
||||
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x38
|
||||
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
|
||||
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
|
||||
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
|
||||
// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
|
||||
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
|
||||
*/
|
||||
#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x52, 0x52, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_OOK_CNT1_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x42
|
||||
// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80,
|
||||
// Descriptions:
|
||||
// MODEM_OOK_CNT1 - OOK control.
|
||||
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
|
||||
// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
|
||||
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
|
||||
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
|
||||
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
|
||||
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
|
||||
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
|
||||
*/
|
||||
#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0xAD, 0x01, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_RSSI_COMP_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x4E
|
||||
// Default values: 0x32,
|
||||
// Descriptions:
|
||||
// MODEM_RSSI_COMP - RSSI compensation value.
|
||||
*/
|
||||
#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CLKGEN_BAND_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x51
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
|
||||
*/
|
||||
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x00
|
||||
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x18
|
||||
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F
|
||||
|
||||
/*
|
||||
// Set properties: RF_PA_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x22
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08, 0x7F, 0x00, 0x5D,
|
||||
// Descriptions:
|
||||
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
|
||||
// PA_PWR_LVL - Configuration of PA output power level.
|
||||
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
|
||||
// PA_TC - Configuration of PA ramping parameters.
|
||||
*/
|
||||
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNTH_PFDCP_CPFF_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x23
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
|
||||
// Descriptions:
|
||||
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
|
||||
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
|
||||
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
|
||||
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
|
||||
*/
|
||||
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_FREQ_CONTROL_INTE_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x40
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
|
||||
// Descriptions:
|
||||
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
|
||||
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
|
||||
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
|
||||
*/
|
||||
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0E, 0xEE, 0xEE, 0x44, 0x44, 0x20, 0xFE
|
||||
|
||||
|
||||
// AUTOMATICALLY GENERATED CODE!
|
||||
// DO NOT EDIT/MODIFY BELOW THIS LINE!
|
||||
// --------------------------------------------
|
||||
|
||||
#ifndef FIRMWARE_LOAD_COMPILE
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { \
|
||||
0x07, RF_POWER_UP, \
|
||||
0x08, RF_GPIO_PIN_CFG, \
|
||||
0x06, RF_GLOBAL_XO_TUNE_2, \
|
||||
0x05, RF_GLOBAL_CONFIG_1, \
|
||||
0x06, RF_INT_CTL_ENABLE_2, \
|
||||
0x08, RF_FRR_CTL_A_MODE_4, \
|
||||
0x05, RF_PREAMBLE_TX_LENGTH_1, \
|
||||
0x05, RF_PREAMBLE_CONFIG_1, \
|
||||
0x07, RF_SYNC_CONFIG_3, \
|
||||
0x05, RF_PKT_CONFIG1_1, \
|
||||
0x05, RF_PKT_FIELD_1_CONFIG_1, \
|
||||
0x10, RF_MODEM_MOD_TYPE_12, \
|
||||
0x05, RF_MODEM_FREQ_DEV_0_1, \
|
||||
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
|
||||
0x0D, RF_MODEM_BCR_OSR_1_9, \
|
||||
0x0B, RF_MODEM_AFC_GEAR_7, \
|
||||
0x05, RF_MODEM_AGC_CONTROL_1, \
|
||||
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
|
||||
0x0C, RF_MODEM_OOK_CNT1_8, \
|
||||
0x05, RF_MODEM_RSSI_COMP_1, \
|
||||
0x05, RF_MODEM_CLKGEN_BAND_1, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
|
||||
0x08, RF_PA_MODE_4, \
|
||||
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
|
||||
0x0C, RF_FREQ_CONTROL_INTE_8, \
|
||||
0x00 \
|
||||
}
|
||||
#else
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
|
||||
#endif
|
||||
|
||||
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
|
||||
#error "This property must be defined!"
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
|
||||
#endif
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA { \
|
||||
Radio_Configuration_Data_Array, \
|
||||
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
|
||||
}
|
||||
|
||||
#endif /* RADIO_CONFIG_H_ */
|
||||
516
RF24configs/radio_config_Si4464_30_915_2GFSK_10_20.h
Normal file
516
RF24configs/radio_config_Si4464_30_915_2GFSK_10_20.h
Normal file
@@ -0,0 +1,516 @@
|
||||
/*! @file radio_config.h
|
||||
* @brief This file contains the automatically generated
|
||||
* configurations.
|
||||
*
|
||||
* @n WDS GUI Version: 3.2.11.0
|
||||
* @n Device: Si4464 Rev.: B1
|
||||
*
|
||||
* @b COPYRIGHT
|
||||
* @n Silicon Laboratories Confidential
|
||||
* @n Copyright 2017 Silicon Laboratories, Inc.
|
||||
* @n http://www.silabs.com
|
||||
*/
|
||||
|
||||
#ifndef RADIO_CONFIG_H_
|
||||
#define RADIO_CONFIG_H_
|
||||
|
||||
// USER DEFINED PARAMETERS
|
||||
// Define your own parameters here
|
||||
|
||||
// INPUT DATA
|
||||
/*
|
||||
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
|
||||
// MOD_type: 3 Rsymb(sps): 10000 Fdev(Hz): 20000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
|
||||
// RF Freq.(MHz): 915 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
|
||||
//
|
||||
// # RX IF frequency is -468750 Hz
|
||||
// # WB filter 3 (BW = 123.48 kHz); NB-filter 3 (BW = 123.48 kHz)
|
||||
//
|
||||
// Modulation index: 4
|
||||
*/
|
||||
|
||||
|
||||
// CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
|
||||
|
||||
|
||||
// CONFIGURATION COMMANDS
|
||||
|
||||
/*
|
||||
// Command: RF_POWER_UP
|
||||
// Description: Command to power-up the device and select the operational mode and functionality.
|
||||
*/
|
||||
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
|
||||
|
||||
/*
|
||||
// Command: RF_GPIO_PIN_CFG
|
||||
// Description: Configures the GPIO pins.
|
||||
*/
|
||||
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_XO_TUNE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x40, 0x00,
|
||||
// Descriptions:
|
||||
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
|
||||
// GLOBAL_CLK_CFG - Clock configuration options.
|
||||
*/
|
||||
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x03
|
||||
// Default values: 0x20,
|
||||
// Descriptions:
|
||||
// GLOBAL_CONFIG - Global configuration settings.
|
||||
*/
|
||||
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
|
||||
|
||||
/*
|
||||
// Set properties: RF_INT_CTL_ENABLE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x01
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x04, 0x00,
|
||||
// Descriptions:
|
||||
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
|
||||
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
|
||||
*/
|
||||
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_FRR_CTL_A_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x02
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x02, 0x09, 0x00,
|
||||
// Descriptions:
|
||||
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
|
||||
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
|
||||
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
|
||||
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
|
||||
*/
|
||||
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_TX_LENGTH_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
|
||||
*/
|
||||
#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x04
|
||||
// Default values: 0x21,
|
||||
// Descriptions:
|
||||
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
|
||||
*/
|
||||
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNC_CONFIG_3
|
||||
// Number of properties: 3
|
||||
// Group ID: 0x11
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x2D, 0xD4,
|
||||
// Descriptions:
|
||||
// SYNC_CONFIG - Sync Word configuration bits.
|
||||
// SYNC_BITS_31_24 - Sync word.
|
||||
// SYNC_BITS_23_16 - Sync word.
|
||||
*/
|
||||
#define RF_SYNC_CONFIG_3 0x11, 0x11, 0x03, 0x00, 0x01, 0xB4, 0x2B
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_CONFIG1_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x06
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
|
||||
*/
|
||||
#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_FIELD_1_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x0F
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
|
||||
*/
|
||||
#define RF_PKT_FIELD_1_CONFIG_1 0x11, 0x12, 0x01, 0x0F, 0x04
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_MOD_TYPE_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
|
||||
// Descriptions:
|
||||
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
|
||||
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
|
||||
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
|
||||
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
|
||||
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x06, 0x1A, 0x80, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_FREQ_DEV_0_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xD3,
|
||||
// Descriptions:
|
||||
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0xBB
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x18
|
||||
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
|
||||
// Descriptions:
|
||||
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
|
||||
// MODEM_MDM_CTRL - MDM control.
|
||||
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
|
||||
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
*/
|
||||
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x10
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_BCR_OSR_1_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x22
|
||||
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
|
||||
// Descriptions:
|
||||
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GEAR - RX BCR loop gear control.
|
||||
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
|
||||
*/
|
||||
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0xF4, 0x01, 0x06, 0x25, 0x00, 0x83, 0x02, 0xC2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AFC_GEAR_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x2C
|
||||
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
|
||||
// Descriptions:
|
||||
// MODEM_AFC_GEAR - RX AFC loop gear control.
|
||||
// MODEM_AFC_WAIT - RX AFC loop wait time control.
|
||||
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
|
||||
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
|
||||
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
|
||||
*/
|
||||
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x0F, 0x16, 0xFE, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_CONTROL_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x35
|
||||
// Default values: 0xE0,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
|
||||
*/
|
||||
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x38
|
||||
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
|
||||
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
|
||||
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
|
||||
// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
|
||||
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
|
||||
*/
|
||||
#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x6D, 0x6D, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2A
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_OOK_CNT1_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x42
|
||||
// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80,
|
||||
// Descriptions:
|
||||
// MODEM_OOK_CNT1 - OOK control.
|
||||
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
|
||||
// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
|
||||
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
|
||||
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
|
||||
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
|
||||
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
|
||||
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
|
||||
*/
|
||||
#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0x82, 0x01, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_RSSI_COMP_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x4E
|
||||
// Default values: 0x32,
|
||||
// Descriptions:
|
||||
// MODEM_RSSI_COMP - RSSI compensation value.
|
||||
*/
|
||||
#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CLKGEN_BAND_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x51
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
|
||||
*/
|
||||
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x08
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x00
|
||||
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x18
|
||||
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PA_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x22
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08, 0x7F, 0x00, 0x5D,
|
||||
// Descriptions:
|
||||
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
|
||||
// PA_PWR_LVL - Configuration of PA output power level.
|
||||
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
|
||||
// PA_TC - Configuration of PA ramping parameters.
|
||||
*/
|
||||
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNTH_PFDCP_CPFF_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x23
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
|
||||
// Descriptions:
|
||||
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
|
||||
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
|
||||
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
|
||||
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
|
||||
*/
|
||||
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_FREQ_CONTROL_INTE_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x40
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
|
||||
// Descriptions:
|
||||
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
|
||||
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
|
||||
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
|
||||
*/
|
||||
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3C, 0x08, 0x00, 0x00, 0x22, 0x22, 0x20, 0xFF
|
||||
|
||||
|
||||
// AUTOMATICALLY GENERATED CODE!
|
||||
// DO NOT EDIT/MODIFY BELOW THIS LINE!
|
||||
// --------------------------------------------
|
||||
|
||||
#ifndef FIRMWARE_LOAD_COMPILE
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { \
|
||||
0x07, RF_POWER_UP, \
|
||||
0x08, RF_GPIO_PIN_CFG, \
|
||||
0x06, RF_GLOBAL_XO_TUNE_2, \
|
||||
0x05, RF_GLOBAL_CONFIG_1, \
|
||||
0x06, RF_INT_CTL_ENABLE_2, \
|
||||
0x08, RF_FRR_CTL_A_MODE_4, \
|
||||
0x05, RF_PREAMBLE_TX_LENGTH_1, \
|
||||
0x05, RF_PREAMBLE_CONFIG_1, \
|
||||
0x07, RF_SYNC_CONFIG_3, \
|
||||
0x05, RF_PKT_CONFIG1_1, \
|
||||
0x05, RF_PKT_FIELD_1_CONFIG_1, \
|
||||
0x10, RF_MODEM_MOD_TYPE_12, \
|
||||
0x05, RF_MODEM_FREQ_DEV_0_1, \
|
||||
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
|
||||
0x0D, RF_MODEM_BCR_OSR_1_9, \
|
||||
0x0B, RF_MODEM_AFC_GEAR_7, \
|
||||
0x05, RF_MODEM_AGC_CONTROL_1, \
|
||||
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
|
||||
0x0C, RF_MODEM_OOK_CNT1_8, \
|
||||
0x05, RF_MODEM_RSSI_COMP_1, \
|
||||
0x05, RF_MODEM_CLKGEN_BAND_1, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
|
||||
0x08, RF_PA_MODE_4, \
|
||||
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
|
||||
0x0C, RF_FREQ_CONTROL_INTE_8, \
|
||||
0x00 \
|
||||
}
|
||||
#else
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
|
||||
#endif
|
||||
|
||||
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
|
||||
#error "This property must be defined!"
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
|
||||
#endif
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA { \
|
||||
Radio_Configuration_Data_Array, \
|
||||
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
|
||||
}
|
||||
|
||||
#endif /* RADIO_CONFIG_H_ */
|
||||
516
RF24configs/radio_config_Si4464_30_915_2GFSK_5_10.h
Normal file
516
RF24configs/radio_config_Si4464_30_915_2GFSK_5_10.h
Normal file
@@ -0,0 +1,516 @@
|
||||
/*! @file radio_config.h
|
||||
* @brief This file contains the automatically generated
|
||||
* configurations.
|
||||
*
|
||||
* @n WDS GUI Version: 3.2.11.0
|
||||
* @n Device: Si4464 Rev.: B1
|
||||
*
|
||||
* @b COPYRIGHT
|
||||
* @n Silicon Laboratories Confidential
|
||||
* @n Copyright 2017 Silicon Laboratories, Inc.
|
||||
* @n http://www.silabs.com
|
||||
*/
|
||||
|
||||
#ifndef RADIO_CONFIG_H_
|
||||
#define RADIO_CONFIG_H_
|
||||
|
||||
// USER DEFINED PARAMETERS
|
||||
// Define your own parameters here
|
||||
|
||||
// INPUT DATA
|
||||
/*
|
||||
// Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0
|
||||
// MOD_type: 3 Rsymb(sps): 5000 Fdev(Hz): 10000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 3
|
||||
// RF Freq.(MHz): 915 API_TC: 29 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1
|
||||
//
|
||||
// # RX IF frequency is -468750 Hz
|
||||
// # WB filter 2 (BW = 103.06 kHz); NB-filter 2 (BW = 103.06 kHz)
|
||||
//
|
||||
// Modulation index: 4
|
||||
*/
|
||||
|
||||
|
||||
// CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 0x07
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 0x03
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 0xF000
|
||||
|
||||
|
||||
// CONFIGURATION COMMANDS
|
||||
|
||||
/*
|
||||
// Command: RF_POWER_UP
|
||||
// Description: Command to power-up the device and select the operational mode and functionality.
|
||||
*/
|
||||
#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80
|
||||
|
||||
/*
|
||||
// Command: RF_GPIO_PIN_CFG
|
||||
// Description: Configures the GPIO pins.
|
||||
*/
|
||||
#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_XO_TUNE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x40, 0x00,
|
||||
// Descriptions:
|
||||
// GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
|
||||
// GLOBAL_CLK_CFG - Clock configuration options.
|
||||
*/
|
||||
#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_GLOBAL_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x00
|
||||
// Start ID: 0x03
|
||||
// Default values: 0x20,
|
||||
// Descriptions:
|
||||
// GLOBAL_CONFIG - Global configuration settings.
|
||||
*/
|
||||
#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
|
||||
|
||||
/*
|
||||
// Set properties: RF_INT_CTL_ENABLE_2
|
||||
// Number of properties: 2
|
||||
// Group ID: 0x01
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x04, 0x00,
|
||||
// Descriptions:
|
||||
// INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
|
||||
// INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
|
||||
*/
|
||||
#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_FRR_CTL_A_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x02
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x02, 0x09, 0x00,
|
||||
// Descriptions:
|
||||
// FRR_CTL_A_MODE - Fast Response Register A Configuration.
|
||||
// FRR_CTL_B_MODE - Fast Response Register B Configuration.
|
||||
// FRR_CTL_C_MODE - Fast Response Register C Configuration.
|
||||
// FRR_CTL_D_MODE - Fast Response Register D Configuration.
|
||||
*/
|
||||
#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_TX_LENGTH_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
|
||||
*/
|
||||
#define RF_PREAMBLE_TX_LENGTH_1 0x11, 0x10, 0x01, 0x00, 0x0A
|
||||
|
||||
/*
|
||||
// Set properties: RF_PREAMBLE_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x10
|
||||
// Start ID: 0x04
|
||||
// Default values: 0x21,
|
||||
// Descriptions:
|
||||
// PREAMBLE_CONFIG - General configuration bits for the Preamble field.
|
||||
*/
|
||||
#define RF_PREAMBLE_CONFIG_1 0x11, 0x10, 0x01, 0x04, 0x31
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNC_CONFIG_3
|
||||
// Number of properties: 3
|
||||
// Group ID: 0x11
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x01, 0x2D, 0xD4,
|
||||
// Descriptions:
|
||||
// SYNC_CONFIG - Sync Word configuration bits.
|
||||
// SYNC_BITS_31_24 - Sync word.
|
||||
// SYNC_BITS_23_16 - Sync word.
|
||||
*/
|
||||
#define RF_SYNC_CONFIG_3 0x11, 0x11, 0x03, 0x00, 0x01, 0xB4, 0x2B
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_CONFIG1_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x06
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
|
||||
*/
|
||||
#define RF_PKT_CONFIG1_1 0x11, 0x12, 0x01, 0x06, 0x02
|
||||
|
||||
/*
|
||||
// Set properties: RF_PKT_FIELD_1_CONFIG_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x12
|
||||
// Start ID: 0x0F
|
||||
// Default values: 0x00,
|
||||
// Descriptions:
|
||||
// PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
|
||||
*/
|
||||
#define RF_PKT_FIELD_1_CONFIG_1 0x11, 0x12, 0x01, 0x0F, 0x04
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_MOD_TYPE_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06,
|
||||
// Descriptions:
|
||||
// MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
|
||||
// MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
|
||||
// MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
|
||||
// MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
|
||||
// MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
|
||||
// MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
|
||||
// MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x03, 0x0D, 0x40, 0x05, 0xC9, 0xC3, 0x80, 0x00, 0x01
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_FREQ_DEV_0_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xD3,
|
||||
// Descriptions:
|
||||
// MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
|
||||
*/
|
||||
#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x5E
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_TX_RAMP_DELAY_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x18
|
||||
// Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20,
|
||||
// Descriptions:
|
||||
// MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
|
||||
// MODEM_MDM_CTRL - MDM control.
|
||||
// MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
|
||||
// MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
|
||||
// MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
// MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
|
||||
*/
|
||||
#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0xC0, 0x00, 0x20, 0x20
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_BCR_OSR_1_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x22
|
||||
// Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0,
|
||||
// Descriptions:
|
||||
// MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
|
||||
// MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
|
||||
// MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
|
||||
// MODEM_BCR_GEAR - RX BCR loop gear control.
|
||||
// MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
|
||||
*/
|
||||
#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x02, 0xEE, 0x00, 0xAE, 0xC3, 0x00, 0x57, 0x02, 0xC2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AFC_GEAR_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x2C
|
||||
// Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0,
|
||||
// Descriptions:
|
||||
// MODEM_AFC_GEAR - RX AFC loop gear control.
|
||||
// MODEM_AFC_WAIT - RX AFC loop wait time control.
|
||||
// MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
|
||||
// MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
|
||||
// MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
|
||||
// MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
|
||||
*/
|
||||
#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x07, 0x29, 0x3F, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_CONTROL_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x35
|
||||
// Default values: 0xE0,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
|
||||
*/
|
||||
#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_AGC_WINDOW_SIZE_9
|
||||
// Number of properties: 9
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x38
|
||||
// Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B,
|
||||
// Descriptions:
|
||||
// MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
|
||||
// MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
|
||||
// MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
|
||||
// MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
|
||||
// MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
|
||||
// MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
|
||||
// MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
|
||||
*/
|
||||
#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0xA4, 0xA4, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2B
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_OOK_CNT1_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x42
|
||||
// Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80,
|
||||
// Descriptions:
|
||||
// MODEM_OOK_CNT1 - OOK control.
|
||||
// MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
|
||||
// MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
|
||||
// MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
|
||||
// MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
|
||||
// MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
|
||||
// MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
|
||||
// MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
|
||||
*/
|
||||
#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0x57, 0x01, 0x80
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_RSSI_COMP_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x4E
|
||||
// Default values: 0x32,
|
||||
// Descriptions:
|
||||
// MODEM_RSSI_COMP - RSSI compensation value.
|
||||
*/
|
||||
#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CLKGEN_BAND_1
|
||||
// Number of properties: 1
|
||||
// Group ID: 0x20
|
||||
// Start ID: 0x51
|
||||
// Default values: 0x08,
|
||||
// Descriptions:
|
||||
// MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
|
||||
*/
|
||||
#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x08
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x00
|
||||
// Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x0C
|
||||
// Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5
|
||||
|
||||
/*
|
||||
// Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
|
||||
// Number of properties: 12
|
||||
// Group ID: 0x21
|
||||
// Start ID: 0x18
|
||||
// Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00,
|
||||
// Descriptions:
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
|
||||
// MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
|
||||
*/
|
||||
#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00
|
||||
|
||||
/*
|
||||
// Set properties: RF_PA_MODE_4
|
||||
// Number of properties: 4
|
||||
// Group ID: 0x22
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x08, 0x7F, 0x00, 0x5D,
|
||||
// Descriptions:
|
||||
// PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
|
||||
// PA_PWR_LVL - Configuration of PA output power level.
|
||||
// PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
|
||||
// PA_TC - Configuration of PA ramping parameters.
|
||||
*/
|
||||
#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
|
||||
|
||||
/*
|
||||
// Set properties: RF_SYNTH_PFDCP_CPFF_7
|
||||
// Number of properties: 7
|
||||
// Group ID: 0x23
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03,
|
||||
// Descriptions:
|
||||
// SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
|
||||
// SYNTH_PFDCP_CPINT - Integration charge pump current selection.
|
||||
// SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
|
||||
// SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
|
||||
// SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
|
||||
*/
|
||||
#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
|
||||
|
||||
/*
|
||||
// Set properties: RF_FREQ_CONTROL_INTE_8
|
||||
// Number of properties: 8
|
||||
// Group ID: 0x40
|
||||
// Start ID: 0x00
|
||||
// Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF,
|
||||
// Descriptions:
|
||||
// FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
|
||||
// FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
|
||||
// FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
|
||||
// FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
|
||||
*/
|
||||
#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x3C, 0x08, 0x00, 0x00, 0x22, 0x22, 0x20, 0xFF
|
||||
|
||||
|
||||
// AUTOMATICALLY GENERATED CODE!
|
||||
// DO NOT EDIT/MODIFY BELOW THIS LINE!
|
||||
// --------------------------------------------
|
||||
|
||||
#ifndef FIRMWARE_LOAD_COMPILE
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { \
|
||||
0x07, RF_POWER_UP, \
|
||||
0x08, RF_GPIO_PIN_CFG, \
|
||||
0x06, RF_GLOBAL_XO_TUNE_2, \
|
||||
0x05, RF_GLOBAL_CONFIG_1, \
|
||||
0x06, RF_INT_CTL_ENABLE_2, \
|
||||
0x08, RF_FRR_CTL_A_MODE_4, \
|
||||
0x05, RF_PREAMBLE_TX_LENGTH_1, \
|
||||
0x05, RF_PREAMBLE_CONFIG_1, \
|
||||
0x07, RF_SYNC_CONFIG_3, \
|
||||
0x05, RF_PKT_CONFIG1_1, \
|
||||
0x05, RF_PKT_FIELD_1_CONFIG_1, \
|
||||
0x10, RF_MODEM_MOD_TYPE_12, \
|
||||
0x05, RF_MODEM_FREQ_DEV_0_1, \
|
||||
0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
|
||||
0x0D, RF_MODEM_BCR_OSR_1_9, \
|
||||
0x0B, RF_MODEM_AFC_GEAR_7, \
|
||||
0x05, RF_MODEM_AGC_CONTROL_1, \
|
||||
0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
|
||||
0x0C, RF_MODEM_OOK_CNT1_8, \
|
||||
0x05, RF_MODEM_RSSI_COMP_1, \
|
||||
0x05, RF_MODEM_CLKGEN_BAND_1, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
|
||||
0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
|
||||
0x08, RF_PA_MODE_4, \
|
||||
0x0B, RF_SYNTH_PFDCP_CPFF_7, \
|
||||
0x0C, RF_FREQ_CONTROL_INTE_8, \
|
||||
0x00 \
|
||||
}
|
||||
#else
|
||||
#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
|
||||
#endif
|
||||
|
||||
// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PATCH { }
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_ARRAY
|
||||
#error "This property must be defined!"
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
|
||||
#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
|
||||
#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT
|
||||
#endif
|
||||
|
||||
#define RADIO_CONFIGURATION_DATA { \
|
||||
Radio_Configuration_Data_Array, \
|
||||
RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \
|
||||
RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET \
|
||||
}
|
||||
|
||||
#endif /* RADIO_CONFIG_H_ */
|
||||
Reference in New Issue
Block a user